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commercial temperature range november 1996 1996 integrated device technology, inc dsc-3034/1 integrated device technology, inc. dual cmos syncfifo ? idt72801 idt72811 idt72821 idt72831 idt72841 features: the 72801 is equivalent to two 72201 256 x 9 fifos the 72811 is equivalent to two 72211 512 x 9 fifos the 72821 is equivalent to two 72221 1024 x 9 fifos the 72831 is equivalent to two 72231 2048 x 9 fifos the 72841 is equivalent to two 72241 4096 x 9 fifos offers optimal combination of large capacity, high speed, design flexibility and small footprint ideal for prioritization, bidirectional, and width expansion applications 15 ns read/write cycle time for the 72801/72811 20 ns read/write cycle time for the 72821/72831/72841 separate control lines and data lines for each fifo separate empty, full, programmable almost-empty and almost-full flags for each fifo enable puts output data lines in high-impedance state space-saving 64-pin thin quad flat pack (tqfp) ?industrial temperature range (-40 o c to +85 o c) is avail- able, tested to military electrical specifications description: 72801/72811/72821/72831/72841 are dual synchronous (clocked) fifos. the device is functionally equivalent to two 72201/72211/72221/72231/72241 fifos in a single package with all associated control, data, and flag lines assigned to separate pins. each of the two fifos (designated fifo a and fifo b) contained in the 72801/72811/72821/72831/72841 has a 9- bit input data port (da0 - da8), db0 - db8) and a 9-bit output data port (qa0 - qa8, qb0 - qb8). each input port is controlled by a free-running clock(wclka, wclkb), and two write enable pins ( wena1 , wena2, wenb1 , wenb2). data is written into each of the two arrays on every rising clock edge of the write clock (wclka wclkb) when the appropriate write enable pins are asserted. the output port of each fifo bank is controlled by its associated clock pin (rclka, rclkb) and two read enable pins ( rena1 , rena2 , renb1 , renb2 ). the read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. an output enable pin ( oea , oeb ) is provided on the read port of each fifo for three-state output control . each of the two fifos has two fixed flags, empty ( efa , efb ) and full ( ffa , ffb ). two programmable flags, almost-empty ( paea , paeb ) and almost-full ( pafa , pafb ), are provided for pin configuration qa 1 qa 2 qa 3 qa 4 qa 5 qa 6 qa 7 qa 8 v cc wena 2 / lda wclka wena 1 rsa da 8 da 7 da 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 qb0 ffb efb oeb renb 2 rclkb renb 1 gnd v cc paeb pafb db 0 db 1 db 2 db 3 db 4 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 pn64-1 qa 0 ffa efa oea rena 2 rclka rena 1 gnd qb 8 qb 7 qb 6 qb 5 qb 4 qb 3 qb 2 qb 1 da 5 da 4 da 3 da 2 da 1 da 0 pafa paea wenb 2 / ldb wclkb wenb 1 rsb db 8 db 7 db 6 db 5 3034 drw 01 tqfp, top view syncfifo is a trademark and the idt logo is a registered trademark of integrated device technology, inc. 5.15 1 for latest information contact idt's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.15 2 commercial temperature 72801/72811/72821/72831/72841 dual cmos syncfifo ? 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 each fifo bank to improve memory utilization. if not pro- grammed, the programmable flags default to empty+7 for paea and paeb , and full-7 for pafa and pafb . the 72801/72811/72821/72831/72841 architecture lends itself to many flexible configurations such as: ? 2-level priority data buffering ? bidirectional operation ? width expansion ? depth expansion this fifo is fabricated using idts high-performance sub- micron cmos technology. functional block diagram wclka wena2 da 0 - da 8 offset register input register ram array 256 x 9, 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9 write control logic write pointer reset logic output register qa 0 - qa 8 rclka read control logic read pointer flag logic 3034 drw 01a wclkb wenb2 db 0 - db 8 offset register input register ram array 256 x 9, 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9 write control logic write pointer reset logic output register qb 0 - qb 8 rclkb read control logic read pointer flag logic
5.15 3 commercial temperature 72801/72811/72821/72831/72841 dual cmos syncfifo ? 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 pin descriptions the 72801/72811/72821/72831/72841s two fifos, referred to as fifo a and fifo b, are identical in every respect. the following description defines the input and output signals for fifo a. the corresponding signal names for fifo b are provided in parentheses. symbol name i/o description d a0 -d a8 a data inputs i 9-bit data inputs to ram array a. d b0 -d b8 b data inputs i 9-bit data inputs to ram array b. rsa , rsb reset i when rsa ( rsb ) is set low, the associated internal read and write pointers of array a (b) are set to the first location; ffa ( ffb ) and pafa ( pafb ) go high, and paea ( paeb ) and efa ( efb ) go low. after power-up, a reset of both fifos a and b is required before an initial write. wclka write clock i data is written into the fifo a (b) on a low-to-high transition of wclka (wclkb) when the wclkb write enable(s) are asserted. wena1 write enable 1 i if fifo a (b) is configured to have programmable flags, wena1 ( wenb1 ) is the only write wenb1 enable pin that can be used. when wena1 ( wenb1 ) is low, data a (b) is written into the fifo on every low-to-high transition wclka (wclkb). if the fifo is configured to have two write enables, wena1 ( wenb1 ) must be low and wena2 (wenb2) must be high to write data into the fifo. data will not be written into the fifo if ffa ( ffb ) is low. wena2/ lda write enable 2/ i fifo a (b) is configured at reset to have either two write enables or programmable flags. if wenb2/ ldb load lda ( ldb ) is high at reset, this pin operates as a second write enable. if wena2/ lda (wenb2/ ldb ) is low at reset this pin operates as a control to load and read the program mable flag offsets for its respective array. if the fifo is configured to have two write enables, wena1 ( wenb1 ) must be low and wena2 (wenb2) must be high to write data into fifo a (b). data will not be written into fifo a (b) if ffa ( ffb ) is low. if the fifo is configured to have programmable flags, lda ( ldb ) is held low to write or read the programmable flag offsets. q a0 -q a8 a data outputs o 9-bit data outputs from ram array a. q b0 -q b8 b data outputs o 9-bit data outputs from ram array b. rclka read clock i data is read from fifo a (b) on a low-to-high transition of rclka (rclkb) when rena1 rclkb ( renb1 ) and rena2 ( renb2 ) are asserted. rena1 read enable 1 i when rena1 ( renb1 ) and rena2 ( renb2 ) are low, data is read from fifo a (b) on every renb1 low-to-high transition of rclka (rclkb). data will not be read from array a (b) if efa ( efb ) is low. rena2 read enable 2 i when rena1 ( renb1 ) and rena2 ( renb2 ) are low, data is read from the fifo a (b) on renb2 every low-to-high transition of rclka (rclkb). data will not be read from array a (b) if the efa (efb) is low. oea output enable i when oea ( oeb ) is low, outputs d a0 -d a8 (d b0 -d b8 ) are active. if oea ( oeb ) is high, the oeb outputs d a0 -d a8 (d b0 -d b8 ) will be in a high-impedance state. efa empty flag o when efa ( efb ) is low, fifo a (b) is empty and further data reads from the output are efb inhibited. when efa ( efb ) is high, fifo a (b) is not empty. efa ( efb ) is synchronized to rclka (rclkb). paea programmable o when paea ( paeb ) is low, fifo a (b) is almost empty based on the offset programmed into paeb almost-empty the appropriate offset register. the default offset at reset is empty+7. paea ( paeb ) is synchro flag nized to rclka (rclkb). pafa programmable o when pafa ( pafb ) is low, fifo a (b) is almost full based on the offset programmed into the pafb almost-full flag appropriate offset register. the default offset at reset is full-7. pafa ( pafb ) is synchronized to wclka (wclkb). ffa full flag o when ffa ( ffb ) is low, fifo a (b) is full and further data writes into the input are inhibited. ffb when ffa ( ffb ) is high, fifo a (b) is not full. ffa ( ffb ) is synchronized to wclka (wclkb). v cc power +5v power supply pin. gnd ground 0v ground pin. 3034 tbl 01
5.15 4 commercial temperature 72801/72811/72821/72831/72841 dual cmos syncfifo ? 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 recommended operating conditions symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v gnd supply voltage 0 0 0 v v ih input high voltage 2.0 v v il input low voltage 0.8 v 3034 tbl 03 capacitance (t a = +25 c, f = 1.0mhz) symbol parameter conditions max. unit c in (2) input capacitance v in = 0v 10 pf c out (1,2) output capacitance v out = 0v 10 pf note: 1. with output deselected ( oea , oeb = high). 3034 tbl 04 idt72801 idt72811 commercial t clk = 15, 20, 25, 35ns symbol parameter min. typ. max. unit i li (1) input leakage current (any input) C1 C1 m a i lo (2) output leakage current C10 10 m a v oh output logic 1 voltage, i oh = C2 ma 2.4 v v ol output logic 0 voltage, i ol = 8 ma 0.4 v i cc (3) active power supply current 270 ma idt72821 idt72831 idt72841 commercial t clk = 20, 25, 35 ns symbol parameter min. typ. max. unit i li (1) input leakage current (any input) C1 C1 m a i lo (2) output leakage current C10 10 m a v oh output logic 1 voltage, i oh = C2 ma 2.4 v v ol output logic 0 voltage, i ol = 8 ma 0.4 v i cc (3) active power supply current 300 ma notes: 1. measurements with 0.4 vin vcc. 2. oea, oeb 3 vih, 0.4 vout vcc. 3. measurements are made with outputs open. tested at f clk = 20mhz. icc limits applicable when using both banks of fifos simultaneously. dc electrical characteristics (commercial: v cc = 5v 10%, t a = 0 c to +70 c) 3034 tbl 06 3034 tbl 05 absolute maximum ratings (1) symbol rating commercial unit v term terminal voltage with C0.5 to +7.0 v respect to gnd t a operating temperature 0 to +70 c t bias temperature under bias C55 to +125 c t stg storage temperature C55 to +125 c i out dc output current 50 ma note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 3034 tbl 02
5.15 5 commercial temperature 72801/72811/72821/72831/72841 dual cmos syncfifo ? 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 ac test conditions in pulse levels gnd to 3.0v input rise/fall times 3ns input timing reference levels 1.5v output reference levels 1.5v output load see figure 1 3034 tbl 08 *includes jig and scope capacitances. figure 1. output load or equivalent circuit ac electrical characteristics (commercial: v cc = 5v 10%, t a = 0 c to +70 c) commercial idt72801l12 idt72801l15 idt72801l20 idt72801l25 idt72801l35 idt72811l12 idt72811l15 idt72811l20 idt72811l25 idt72811l35 idt72821l12 idt72821l15 idt72821l20 idt72821l25 idt72821l35 idt72831l12 idt72831l15 idt72831l20 idt72831l25 idt72831l35 idt72841l12 idt72841l15 idt72841l20 idt72841l25 idt72841l35 symbol parameter min. max. min. max. min. max. min. max. min. max. unit f s clock cycle frequency 83.3 66.7 50 40 28.6 mhz t a data access time 2 8 2 10 2 12 3 15 3 20 ns t clk clock cycle time 12 15 20 25 35 ns t clkh clock high time 5 6 8 10 14 ns t clkl clock low time 5 6 8 10 14 ns t ds data set-up time 3 4 5 6 8 ns t dh data hold time 0 1 1 1 2 ns t ens enable set-up time 3 4 5 6 8 ns t enh enable hold time 0 1 1 1 2 ns t rs reset pulse width (1) 12 15 20 25 35 ns t rss reset set-up time 12 15 20 25 35 ns t rsr reset recovery time 12 15 20 25 35 ns t rsf reset to flag time and output time 12 15 20 25 35 ns t olz output enable to output in low-z (2) 0 0 0 0 0ns t oe output enable to output valid 3 7 3 8 3 10 3 13 3 15 ns t ohz output enable to output in high-z (2) 3 7 3 8 310 313 315ns t wff write clock to full flag 8 10 12 15 20 ns t ref read clock to empty flag 8 10 12 15 20 ns t paf write clock to programmable almost-full flag 8 10 12 15 20 ns t pae read clock to programmable almost-empty flag 8 10 12 15 20 ns t skew1 skew time between read 5 6 8 10 12 ns clock and write clock for empty flag and full flag t skew2 skew time between read clock 22 28 35 40 42 ns and write clock for programmable almost-empty flag and programmable almost-full flag notes: 3034 tbl 07 1. pulse widths less than minimum values are not allowed. 2. values guaranteed by design, not currently tested. 30pf* 1.1k 5v 680 w d.u.t. 3034 drw 03
5.15 6 commercial temperature 72801/72811/72821/72831/72841 dual cmos syncfifo ? 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 read clock (rclka, rclkb) data can be read from array a (b) on the the low-to-high transition of rclka (rclkb). the empty flag efa ( efb ) and programmable almost-empty flag paea ( paeb ) are synchronized with re- spect to the low-to-high transition of rclka (rclkb). the write and read clock can be asynchronous or coinci- dent. read enables ( rena1 rena1 , rena2 rena2 , renb1 renb1 , renb2 renb2 ) when both read enables rena1 , rena2 ( renb1 , renb2 ) are low, data is read from array a (b) to the output register on the low-to-high transition of the read clock rclka (rclkb). when either of the two read enable rena1 , rena2 ( renb1 , renb2 ) associated with fifo a (b) is high, the output register holds the previous data and no new data is allowed to be loaded into the register. when all the data has been read from fifo a (b), the empty flag efa ( efb ) will go low, inhibiting further read operations. once a valid write operation has been accom- plished, efa ( efb ) will go high after t ref and a valid read can begin. the read enables rena1 , rena2 ( renb1 , renb2 ) are ignored when fifo a (b) is empty. output enable ( oea oea , oeb oeb ) when output enable oea ( oeb ) is enabled (low), the parallel output buffers of fifo a (b) receive data from their respective output register. when output enable oea ( oeb ) is disabled (high), the qa (qb) output data bus is in a high-impedance state. write enable 2/load (wena2/ lda lda , wenb2/ ldb ldb ) this is a dual-purpose pin. fifo a (b) is configured at reset to have programmable flags or to have two write enables, which allows depth expansion. if wena2/ lda (wenb2/ ldb ) is set high at reset rsa = low ( rsb = low), this pin operates as a second write enable pin. if fifo a (b) is configured to have two write enables, when write enable 1 wena1 ( wenb1 ) is low and wena2/ lda (wenb2/ ldb ) is high, data can be loaded into the input register and ram array on the low-to-high transition of every write clock wclka (wclkb). data is stored in the array sequentially and independently of any on-going read operation. in this configuration, when wena1 ( wenb1 ) is high and/ or wena2/ lda (wenb2/ ldb ) is low, the input register of array a holds the previous data and no new data is allowed to be loaded into the register. to prevent data overflow, the full flag ffa ( ffb ) will go low, inhibiting further write operations. upon the completion of a valid read cycle, ffa ( ffb ) will go high after t wff , al- lowing a valid write to begin. wena1 , ( wenb1 ) and wena2/ lda (wenb2/ ldb ) are ignored when the fifo is full. fifo a (b) is configured to have programmable flags when the wena2/ lda (wenb2/ ldb ) is set low at reset rsa = low ( rsb = low). each fifo contains four 8-bit offset registers which can be loaded with data on the inputs, or read on the outputs. see figure 3 for details of the size of the registers and the default values. signal descriptions fifo a and fifo b are identical in every respect. the following description explains the interaction of input and output signals for fifo a. the corresponding signal names for fifo b are provided in parentheses. inputs: data in (d a0 ?d a8 , d b0 ?d b8 ) ? d a0 - d a8 are the nine data inputs for memory array a. d b0 - d b8 are the nine data inputs for memory array b. controls: reset ( rsa rsa , rsb rsb ) reset of fifo a (b) is accomplished whenever rsa ( rsb ) input is taken to a low state. during reset, the internal read and write pointers associated with the fifo are set to the first location. a reset is required after power-up before a write operation can take place. the full flag ffa ( ffb ) and programmable almost-full flag pafa ( pafb ) will be reset to high after t rsf . the empty flag efa ( efb ) and programmable almost-empty flag paea ( paeb ) will be reset to low after t rsf . during reset, the output register is initialized to all zeros and the offset registers are initialized to their default values. write clock (wclka, wclkb) a write cycle to array a (b) is initiated on the low-to-high transition of wclka (wclkb). data set-up and hold times must be met with respect to the low-to-high transition of wclka (wclkb). the full flag ffa ( ffb ) and programmable almost-full flag pafa ( pafb ) are synchronized with respect to the low-to- high transition of the write clock wclka (wclkb). the write and read clocks can be asynchronous or coinci- dent. write enable 1 ( wena1 wena1 , wenb1 wenb1 ) if fifo a (b) is con- figured for programmable flags, wena1 ( wenb1 ) is the only enable control pin. in this configuration, when wena1 ( wenb1 ) is low, data can be loaded into the input register of ram array a (b) on the low-to-high transition of every write clock wclka (wclkb). data is stored in array a (b) sequentially and independently of any on-going read operation. in this configuration, when wena1 ( wenb1 ) is high, the input register holds the previous data and no new data is allowed to be loaded into the register. if the fifo is configured to have two write enables, which allows for depth expansion. see write enable 2 paragraph below for operation in this configuration. to prevent data overflow, ffa ( ffb ) will go low, inhibiting further write operations. upon the completion of a valid read cycle, the ffa ( ffb ) will go high after t wff , allowing a valid write to begin. wena1 ( wenb1 ) is ignored when fifo a (b) is full.
5.15 7 commercial temperature 72801/72811/72821/72831/72841 dual cmos syncfifo ? 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 lda wena1 wclka (1) operation on fifo a ldb wenb1 wclkb (1) operation on fifo b 0 0 empty offset (lsb) empty offset (msb) full offset (lsb) full offset (msb) 0 1 no operation 1 0 write into fifo 1 1 no operation note: 3034 drw 04 1. the same selection sequence applies to reading from the registers. rena1 and rena2 ( renb1 and renb2 ) are enabled and read is per- formed on the low-to-high transition of rclka (rclkb). figure 3. offset register formats and default values for the a and b fifos if fifo a (b) is configured to have programmable flags, when the wena1 ( wenb1 ) and wena2/ lda (wenb2/ ldb ) are set low, data on the da (db) inputs are written into the empty (least significant bit) offset register on the first low- to-high transition of the wclka (wclkb). data are written into the empty (most significant bit) offset register on the second low-to-high transition of wclka (wclkb), into the full (least significant bit) offset register on the third transition, and into the full (most significant bit) offset register on the fourth transition. the fifth transition of wclka (wclkb) again writes to the empty (least significant bit) offset register. however, writing all offset registers does not have to occur at one time. one or two offset registers can be written and then by bringing lda ( ldb ) high, fifo a (b) is returned to normal read/write operation. when lda ( ldb ) is set low, and wena1 ( wenb1 ) is low, the next offset register in sequence is written. the contents of the offset registers can be read on the qa (qb) outputs when wena2/ lda (wenb2/ ldb ) is set low and both read enables rena1 , rena2 ( renb1 , renb2 ) are set low. data can be read on the low-to-high transition of the read clock rclka (rclkb). a read and write should not be performed simultaneously to the offset registers. figure 2. writing to offset registers for fifos a and b 87 0 empty offset (lsb) reg. default value 007h 80 full offset (lsb) reg. default value 007h 7 80 empty offset (lsb) default value 007h 80 full offset (lsb) default value 007h 72801 - 256 x 9 x 2 72811 - 512 x 9 x 2 7 7 80 (msb) 1 00 87 0 empty offset (lsb) reg. default value 007h 80 full offset (lsb) reg. default value 007h 7 80 empty offset (lsb) default value 007h 80 full offset (lsb) default value 007h 72831 - 2048 x 9 x 2 72841 - 4096 x 9 x 2 7 7 8080 (msb) 0000 2 (msb) 000 3 8080 (msb) 0000 2 (msb) 000 3 80 8 0 80 (msb) 1 0 87 0 empty offset (lsb) reg. default value 007h 80 full offset (lsb) reg. default value 007h 7 72821 - 1024 x 9 x 2 80 (msb) 00 1 80 (msb) 00 1 3034 drw 05
5.15 8 commercial temperature 72801/72811/72821/72831/72841 dual cmos syncfifo ? 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 outputs: full flag ( ffa ffa , ffb ffb ) ffa ( ffb ) will go low, inhibiting further write operations, when array a (b) is full. if no reads are performed after reset, ffa ( ffb ) will go low after 256 writes to the 72801's fifo a (b), 512 writes to the 72811's fifo a (b), 1024 writes to the 72821's fifo a (b), 2048 writes to the 72831's fifo a (b), or 4096 writes to the 72841's fifo a (b). ffa ( ffb ) is synchronized with respect to the low-to- high transition of the write clock wclka (wclkb). empty flag ( efa efa , efb efb ) efa ( efb ) will go low, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating that array a (b) is empty. efa ( efb ) is synchronized with respect to the low-to- high transition of the read clock rclka (rclkb). programmable almost?ull flag ( pafa pafa , pafb pafb ) pafa ( pafb ) will go low when the amount of data in array a (b) reaches the almost-full condition. if no reads are performed after reset, pafa ( pafb ) will go low after (256-m) writes to the 72801's fifo a (b), (512-m) writes to the 72811's fifo a (b), (1024-m) writes to the 72821's fifo a (b), (2048-m) table 1: status flags for a and b fifos number of words in array a ffa ffa pafa pafa paea paea efa efa number of words in array b ffb ffb pafb pafb paeb paeb efb efb 72801 72811 72821 000hhll 1 to n (1) 1 to n (1) 1 to n (1) hhlh (n+1) to (256-(m+1)) (n+1) to (512-(m+1)) (n+1) to (1024-(m+1)) h h h h (256-m) (2) to 255 (512-m) (2) to 511 (1024-m) (2) to 1023 h l h h 256 512 1024 l l h h number of words in array a ffa ffa pafa pafa paea paea efa efa number of words in array b ffb ffb pafb pafb paeb paeb efb efb 72831 72841 00hhll 1 to n (1) 1 to n (1) hhlh (n+1) to (2048-(m+1)) (n+1) to (4096-(m+1)) h h h h (2048-m) (2) to 2047 (4096-m) (2) to 4095 h l h h 2048 4096 l l h h notes: 3034 tbl 09 1. n = empty offset (n = 7 default value) 2. m = full offset (m = 7 default value) writes to the 72831's fifo a (b), or (4096-m) writes to the 72841's fifo a (b). ffa ( ffb ) is synchronized with respect to the low-to- high transition of the write clock wclka (wclkb). the offset m is defined in the full offset registers. if there is no full offset specified, pafa ( pafb ) will go low at full-7 words. pafa ( pafb ) is synchronized with respect to the low-to- high transition of the write clock wclka (wclkb). programmable almost?mpty flag ( paea paea , paeb paeb ) paea ( paeb ) will go low when the read pointer is "n+1" locations less than the write pointer. the offset "n" is defined in the empty offset registers. if no reads are performed after reset, paea ( paeb ) will go high after "n+1" writes to fifo a (b). if there is no empty offset specified, paea ( paeb ) will go low at empty+7 words. paea ( paeb ) is synchronized with respect to the low-to- high transition of the read clock rclka (rclkb). data outputs (qa 0 ?qa 8, qb 0 ?qb 8 ) qa 0 - qa 8 are the nine data outputs for memory array a, qb 0 - qb 8 are the nine data outputs for memory array b .
5.15 9 commercial temperature 72801/72811/72821/72831/72841 dual cmos syncfifo ? 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 t rs t rsr rsa ( rsb ) rena1 , rena2 ( renb1 , renb2 ) t rsf t rsf oea ( oeb ) = 1 oea ( oeb ) = 0 (2) efa , paea ( efb , paeb ) ffa , pafa ( ffa , pafa ) qa 0 - qa 8 (qb 0 - qb 8 ) 3034 drw 06 wena1 ( wenb1 ) t rss t rsf t rsr t rss t rsr t rss wena2/ lda (wenb2/ ldb ) (1) notes: 1. holding wena2/ lda (wenb2/ ldb ) high during reset will make the pin act as a second write enable pin. holding wen2/ lda (wenb2/ ldb ) low during reset will make the pin act as a load enable for the programmable flag offset registers. 2. after reset, qa 0 - qa 8 (qb 0 - qb 8 ) will be low if oea ( oeb ) = 0 and tri-state if oea ( oeb ) = 1. 3. the clocks rclka, wclka (rclkb, wclkb) can be free-running during reset. figure 4. reset timing
5.15 10 commercial temperature 72801/72811/72821/72831/72841 dual cmos syncfifo ? 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 figure 5. write cycle timing t dh t enh t skew1 (1) t clk t clkh t clkl t ds t ens t wff t wff wclka (wclkb) (da 0 - da 8 db 0 - db 8 ) wena1 ( wenb1 ) wena2 (wenb2) (if applicable) ffa ( ffb ) rclka (rclkb) rena1 , rena2 ( renb1 , renb2) no operation no operation 3034 drw 07 data in valid note: 1. t skew1 is the minimum time between a rising rclka (rclkb) edge and a rising wclka (wclkb) edge for ffa ( ffb ) to change during the current clock cycle. if the time between the rising edge of rclka (rclkb) and the rising edge of wclka (wclkb) is less than t skew1 , then ffa ( ffb ) may not change state until the next wclka (wclkb) edge.
5.15 11 commercial temperature 72801/72811/72821/72831/72841 dual cmos syncfifo ? 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 t enh t ens no operation t olz valid data t skew1 (1) t clk t clkh t clkl t ref t ref t a t oe t ohz rclka (rclkb) rena1 , rena2 ( renb1 , renb2 ) efa ( efb ) qa 0 - qa 8 (qb 0 - qb 8 ) oea ( oeb ) wclka, wclkb wena1 ( wenb1 ) wena2 (wenb2) 3034 drw 08 note: 1. t skew1 is the minimum time between a rising wclka (wclkb) edge and a rising rclka (rclkb) edge for efa ( efb ) to change during the current clock cycle. if the time between the rising edge of rclka (rclkb) and the rising edge of wclka (wclkb) is less than t skew1 , then efa ( efb ) may not change state until the next rclka (rclkb) edge. figure 6. read cycle timing
5.15 12 commercial temperature 72801/72811/72821/72831/72841 dual cmos syncfifo ? 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 t ds d 0 (first valid t skew1 d 0 d 1 d 3 d 2 d 1 t ens t frl (1) t ref t a t olz t oe t a wclka (wclkb) da 0 - da 8 (db 0 - db 8 ) wena2 (wenb2) (if applicable) rclka (rclkb) efa ( efb ) rena1 , rena2 ( renb1 , renb2 ) qa 0 - qa 8 (qb 0 - qb 8 ) oea ( oeb ) wena1 ( wenb1 ) 3034 drw 09 note: 1. when t skew1 3 minimum specification, t frl = t clk + t skew1 when t skew1 < minimum specification, t frl = 2t clk + t skew1 or t clk + t skew1 the latency timings apply only at the empty boundary ( efa , efb = low). figure 7. first data word latency timing
5.15 13 commercial temperature 72801/72811/72821/72831/72841 dual cmos syncfifo ? 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 figure 8. full flag timing t skew1 t ds t skew1 data write t ds t enh t enh next data read data read wclka (wclkb) da 0 - da 8 (db 0 - db 8 ) ffa ( ffb ) wena1 ( wenb1 ) wena2 (wenb2) (if applicable) rclka (rclkb) rena1 ( renb2 ) qa 0 - qa 8 (qb 0 - qb 8 ) t wff t wff t wff t ens t ens data in output register oea ( oeb ) low no write no write 3034 drw 10 t a t a
5.15 14 commercial temperature 72801/72811/72821/72831/72841 dual cmos syncfifo ? 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 t a t ds t ds data write 1 t ens t enh t ens t enh t ens t enh t ens t enh data write 2 (1) wclka (wclkb) da 0 - da 8 (db 0 - db 8 ) rclka (rlckb) efa ( efb ) rena1 , rena2 ( renb1 , renb2 ) oea ( oeb ) qa 0 - qa 8 (qb 0 - qb 8 ) data read t skew1 t frl t ffl data in output register (1) t skew1 low wena2 (wenb2) (if applicable) t ref t ref t ref w ena1 , ( wenb1 ) 3034 drw 11 note: 1. when t skew1 3 minimum specification, t frl maximum = t clk + t skew1 when t skew1 < minimum specification, t frl maximum = 2t clk + t skew1 or t clk + t skew1 the latency timings apply only at at the empty boundary ( efa , efb = low). figure 9. empty flag timing
5.15 15 commercial temperature 72801/72811/72821/72831/72841 dual cmos syncfifo ? 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 t ens t enh t ens t enh t ens t enh wclka (wclkb) wena1 ( wenb1 wena2 (wenb2) (if applicable) pafa ( pafb ) rclka (rclkb) rena1 , rena2 ( renb1 , renb2 ) (4) (1) t paf full - (m+1) words in fifo full - m words in fifo (2) t clkh t clkl t skew2 (3) t paf 3034 drw 12 notes: 1. paf offset = m. 2. (256-m) words for the 72801, (512-m) words the 72811, (1024-m) words for the 72821, (2048-m) words for the 72831, or (4096-m) words for the 72841. 3. t skew2 is the minimum time between a rising rclka (rclkb) edge and a rising wclka (wclkb) edge for pafa ( pafb ) to change during that clock cycle. if the time between the rising edge of rclka (rclkb) and the rising edge of wclka (wclkb) is less than t skew2 , then pafa ( pafb ) may not change state until the next wclka (wclkb) rising edge. 4. if a write is performed on this rising edge of the write clock, there will be full - (m-1) words in fifo a (b) when pafa ( pafb ) goes low. figure 10. programmable full flag timing
5.15 16 commercial temperature 72801/72811/72821/72831/72841 dual cmos syncfifo ? 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 figure 11. programmable empty flag timing wclka (wclkb) wena1 ( wenb1 ) wena2 (wenb2) (if applicable) paea , paeb rclka (rclkb) rena1 , rena2 ( renb1 , renb2 ) t ens t enh t ens t enh t skew2 (2) t ens t enh t pae t pae (3) (1) n words in fifo n+1 words in fifo t clkh t clkl 3034 drw 13 notes: 1. pae offset = n. 2. t skew2 is the minimum time between a rising wclka (wclkb) edge and a rising rclka (rclkb) edge for paea ( paeb ) to change during that clock cycle. if the time between the rising edge of wclka (wclkb) and the rising edge of rclka (rclkb) is less than t skew2 , then paea ( paeb ) may not change state until the next rclka (rclkb) rising edge. 3. if a read is performed on this rising edge of the read clock, there will be empty + (n-1) words in fifo a (b) when paea ( paeb ) goes low.
5.15 17 commercial temperature 72801/72811/72821/72831/72841 dual cmos syncfifo ? 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 t ens t enh t ens t ds t dh wclka (wclkb) lda ( ldb ) w ena1 ( wenb1 ) da 0 - da 7 (db 0 - db 7 ) paf offset (msb) paf offset (lsb) pae offset (msb) pae offset (lsb) t clk t clkl t clkh 3034 drw 14 figure 12. write offset register timing t ens t enh t ens data in output register empty offset (lsb) empty offset (msb) full offset (lsb) full offset (msb) rclka (rclkb) lda ( ldb ) rena1 , rena2 ( renb1 , renb2 ) qa 0 - qa 7 (qb 0 - qb 7 ) t clk t a t clkl t clkh 3034 drw 15 figure 13. read offset register timing
5.15 18 commercial temperature 72801/72811/72821/72831/72841 dual cmos syncfifo ? 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 operating configurations single device configuration when fifo a (b) is in a single device configuration, the read enable 2 rena2 ( renb2 ) control input can be grounded (see figure 14). in width expansion configuration ? word width may be increased simply by connecting the corresponding input control signals of fifos a and b. a composite flag should be created for each of the end-point status flags efa and efb , also ffa and ffb ). the partial status flags paea , pafb , paea and pafb can be detected from any one device. figure 15 demonstrates an 18-bit word width using the two fifos contained in one idt72801/72811/72821/72831/72841. any word width can be attained by adding additional idt2801/ 72811/72821/72831/72841s. when the idt2801/72811/72821/72831/72841 is in a width expansion configuration, the read enable 2 ( rena2 and renb2 ) control inputs can be grounded (see figure 15). in this configuration, the write enable 2/load (wena2/ lda , wenb2/ ldb ) pins are set low at reset so that the pin operates as a control to load and read the programmable flag offsets. figure 15. block diagram of the two fifos contained in one 72801/72811/72821/72831/72841configured for an 18-bit width-expansion this configuration, the write enable 2/load wena2/ lda (wenb2/ ldb ) pin is set low at reset so that the pin operates as a control to load and read the programmable flag offsets. figure 14. block diagram of one of the 72801/72811/72821/72831/72841's two fifos configured as a single device qa 0 - qa 8 (qb 0 - qb 8 ) da 0 - da 8 (db 0 - db 8 ) rsa ( rsb ) rclka (rclkb) rena1 ( renb1 ) oea ( oeb ) efa ( efb ) paea ( paeb ) rena2 ( renb2 ) wclka (wclkb) wena1 ( wenb1 ) wena2/ lda (wenb2/ ldb ) ffa ( ffb ) pafa ( pafb ) idt 72801 72811 72821 72831 72841 fifo a (b) 3034 drw 16 data in write clock 18 9 rsb read clock 9 18 renb2 rena2 write enable ffa efb output enable read enable 9 write enable/load ffb efa rsa ram array b 256x9 512x9 1024x9 2048x9 4096x9 ram array a 256x9 512x9 1024x9 2048x9 4096x9 ? ? data out rclka empty flag renb1 rena 1 oeb oea1 rclkb wclka wclkb wena1 wenb1 da0 - da8 db0 - db8 qa0 - qa8 qb0 - qb8 wena2/ lda 2wenb2/ ldb reset ? 9 full flag 3034 drw 17
5.15 19 commercial temperature 72801/72811/72821/72831/72841 dual cmos syncfifo ? 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 type, sending one kind to fifo a and the other kind to fifo b. then, at the outputs, each data type is transferred to its appropriate destination. additional idt2801/72811/72821/ 72831/72841s permit more than two priority levels. priority buffering is particularly useful in network applications. two priority data buffer configuration the two fifos contained in the idt2801/72811/72821/ 72831/72841 can be used to prioritize two different types of data shared on a system bus. when writing from the bus to the fifo, control logic sorts the intermixed data according to figure 16. block diagram of two priority configuration ram array a processor data d a0 -d a8 q a0 -q a8 oea rena address idt 72801 72811 72821 72831 72841 d b0 -d b8 q b0 -q b8 oeb2 wenb1 control logic ram 9-bit bus rclka wclkb control 9 9 9 9 wclka wena1 ram array b renb1 clock rclkb wenb2 renb2 wena2 rena2 v cc v cc 9 9 voice processing card data i/o data clock control logic address control image processing card data i/o data clock control logic address control 3034 drw 18
5.15 20 commercial temperature 72801/72811/72821/72831/72841 dual cmos syncfifo ? 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 bidiriectional configuration the two fifos of the idt2801/72811/72821/72831/72841 can be used to buffer data flow in two directions. in the example that follows, a processor can write data to a peripheral controller via fifo a, and, in turn, the peripheral controller can write the processor via fifo b. figure 17. block diagram of bidirectional configuration ram array a processor peripheral controller data da0-da8 qa0-qa8 data oea rena1 address i/o data idt 72801 72811 72821 72831 72841 db0-db8 qb0-qb8 oeb wenb1 control logic ram 9-bit bus 9-bit bus rclka wclkb control 9 9 9 9 9 9 wclka wena1 ram array b renb1 clock rclkb dma clock control logic address control 9 wenb2 renb2 wena2 rena2 v cc v cc 3034 drw 19
5.15 21 commercial temperature 72801/72811/72821/72831/72841 dual cmos syncfifo ? 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 depth expansion ? idt2801/72811/72821/72831/ 72841 can be adapted to applications that require greater than 256/512/1024/2048/4096 words. the existence of double enable pins on the read and write ports allow depth expansion. the write enable 2/load (wena2, wenb2) pins are used as a second write enables in a depth expansion configuration, thus the programmable flags are set to the default values. depth expansion is possible by using one enable input for system control while the other enable input is controlled by expansion logic to direct the flow of data. a typical application ordering information would have the expansion logic alternate data access from one device to the next in a sequential manner. the idt2801/ 72811/72821/72831/72841 operates in the depth expansion configuration when the following conditions are met: 1. wena2/ lda and wenb2/ ldb pins are held high dur- ing reset so that these pins operate as second write enables. 2. external logic is used to control the flow of data. please see the application note" depth expansion of idt's synchronous fifos using the ring counter approach" for details of this configuration. 3034 drw 20 xxxxx idt device type l xx pf power speed package process/ temperature range clock cycle time(tclk), speed in nanoseconds blank commercial (0 c to +70 c) thin quad flat pack (tqfp) 12 15 20 25 35 low power 72801 256 x 9 dual fifo 72811 512 x 9 dual fifo 72821 1024 x 9 dual fifo 72831 2048 x 9 dual fifo 72841 4096 x 9 dual fifo

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